3-27 mt8812 8 x 12 analog switch array features ? internal control latches and address decoder ? short set-up and hold times ? wide operating voltage: 4.5v to 14.5v ? 14vpp analog signal capability ?r on 65 w max. @ v dd =14v, 25c ? d r on 10 w @ v dd =14v, 25c ? full cmos switch for low distortion ? minimum feedthrough and crosstalk ? low power consumption iso-cmos technology applications ? pbx systems ? mobile radio ? test equipment /instrumentation ? analog/digital multiplexers ? audio/video switching description the mitel mt8812 is fabricated in mitels iso- cmos technology providing low power dissipation and high reliability. the device contains a 8 x12 array of crosspoint switches along with a 7 to 96 line decoder and latch circuits. any one of the 96 switches can be addressed by selecting the appropriate seven input bits. the selected switch can be turned on or off by applying a logical one or zero to the data input. ordering information mt8812ac 40 pin ceramic dip MT8812AE 40 pin plastic dip mt8812ap 44 pin plcc 0 to 70c figure 1 - functional block diagram 7 to 96 decoder latches 8 x 12 switch array ax0 ax1 ay0 ay1 ay2 strobe data reset vdd vss xi i/o (i=0-11) yi i/o (i=0-7) 11 96 96 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ax2 ax3 issue 5 november 1988 iso-cmos
mt8812 iso-cmos 3-28 figure 2 - pin connections * plastic dip and cerdip only. pin description pin #* name description 1y3 y3 analog (input/output): this is connected to the y3 column of the switch array. 2ay2 y2 address line (input) . 3reset master reset (input): this is used to turn off all switches. active high. 4,5 ax3,ax0 x3 and x0 address lines (inputs) . 6,7 nc no connection. 8-13 x6-x11 x6-x11 analog (inputs/outputs): these are connected to the x6-x11 rows of the switch array. 14 nc no connection. 15 y7 y7 analog (input/output): this is connected to the y7 column of the switch array. 16 nc no connection. 17 y6 y6 analog (input/output): this is connected to the y6 column of the switch array. 18 strobe strobe (input) : enables function selected by address and data. address must be stable before strobe goes high and data must be stable on the falling edge of the strobe. active high. 19 y5 y5 analog (input/output): this is connected to the y5 column of the switch array. 20 v ss ground reference. 21 y4 y4 analog (input/output): this is connected to the y4 column of the switch array. 22, 23 ax1,ax2 x1 and x2 address lines (inputs) . 24, 25 ay0,ay1 y0 and y1 address lines (inputs) . 26, 27 nc no connection. 28 - 33 x5-x0 x5-x0 analog (inputs/outputs): these are connected to the x5-x0 rows of the switch array. 34 nc no connection. 35 y0 y0 analog (input/output) : this is connected to the y0 column of the switch array. 36 nc no connection. 37 y1 y1 analog (input/output) : this is connected to the y1 column of the switch array. 38 data data (input) : a logic high input will turn on the selected switch and a logic low will turn off the selected switch. active high. 39 y2 y2 analog (input/output) : this is connected to the y2 column of the switch array. 40 v dd positive power supply. 40 pin cerdip/plastic dip 44 pin plcc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 ay2 reset ax3 ax0 nc nc x6 x7 x8 x9 x10 x11 nc y7 nc y6 strobe y5 vss y3 y2 data y1 nc y0 nc x0 x1 x2 x3 x4 x5 nc nc ay1 ay0 ax2 ax1 y4 vdd nc nc x6 x7 x8 x9 x10 x11 nc nc nc y7 y6 strobe y5 vss ax1 ax2 ay0 ay1 nc y4 1 65432 44434241 40 7 8 9 10 11 12 13 14 15 16 39 38 37 36 35 34 33 32 31 30 23 18 19 20 21 22 24 25 26 27 28 17 29 nc nc x0 x1 x2 x3 x4 x5 nc nc nc y0 y1 data y2 vdd y3 ay2 reset ax3 ax0 nc
iso-cmos mt8812 3-29 functional description the mt8812 is an analog switch matrix with an array size of 8 x 12. the switch array is arranged such that there are 8 columns by 12 rows. the columns are referred to as the y input/output lines and the rows are the x input/output lines. the crosspoint analog switch array will interconnect any x line with any y line when turned on and provide a high degree of isolation when turned off. the control memory consists of a 96 bit write only ram in which the bits are selected by the address input lines (ay0-ay2, ax0-ax3). data is presented to the memory on the data input line. data is asynchro-nously written into memory whenever the strobe input is high and is latched on the falling edge of strobe. a logical 1 written into a memory cell turns the corresponding crosspoint switch on and a logical 0 turns the crosspoint off. only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. the remaining switches retain their previous states. any combination of x and y lines can be interconnected by establishing appropriate patterns in the control memory. a logical 1 on the reset input line will asynchronously return all memory locations to logical 0 turning off all crosspoint switches. address decode the seven address lines along with the strobe input are logically anded to form an enable signal for the resettable transparent latches. the data input is buffered and is used as the input to all latches. to write to a location, reset must be low while the address and data lines are set up. then the strobe input is set high and then low causing the data to be latched. the data can be changed while strobe is high, however, the corresponding switch will turn on and off in accordance with the data. data must be stable on the falling edge of strobe in order for correct data to be written to the latch.
mt8812 iso-cmos 3-30 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? dc electrical characteristics are over recommended temperature range. ? typical figures are at 25c and are for design aid only; not guaranteed and not subject to production testing. absolute maximum ratings * - voltages are with respect to v ss unless otherwise stated. parameter symbol min max units 1 supply voltage v dd v ss -0.3 -0.3 16.0 v dd +0.3 v v 2 analog input voltage v ina -0.3 v dd +0.3 v 3 digital input voltage v in v ss -0.3 v dd +0.3 v 4 current on any i/o pin i 15 ma 5 storage temperature t s -65 +150 c 6 package power dissipation plastic dip cerdip p d p d 0.6 1.0 w w recommended operating conditions - voltages are with respect to v ss unless otherwise stated. characteristics sym min typ max units test conditions 1 operating temperature t o 025 70 c 2 supply voltage v dd 4.5 14.5 v 3 analog input voltage v ina v ss v dd v 4 digital input voltage v in v ss v dd v dc electrical characteristics ? - voltages are with respect to v ss =0v, v dd =14v unless otherwise stated. characteristics sym min typ ? max units test conditions 1 quiescent supply current i dd 1100 a all digital inputs at v in =v ss or v dd 7 15 ma all digital inputs at v in =2.4v 2 off-state leakage current (see g.9 in appendix) i off 1 500 na iv xi - v yj i = v dd - v ss see appendix, fig. a.1 3 input logic 0 level v il 0.8 v 4 input logic 1 level v ih 2.4 v 5 input leakage (digital pins) i leak 0.1 10 a all digital inputs at v in = v ss or v dd dc electrical characteristics- switch resistance - v dc is the external dc offset applied at the analog i/o pins. characteristics sym 25c 60c 70c units test conditions typ max typ max typ max 1 on-state v dd =14v resistance v dd =12v v dd =10v v dd = 5v (see g.1, g.2, g.3 in appendix) r on 45 60 65 145 65 85 95 220 75 95 110 260 w w w w v ss =0v,v dc =v dd /2, iv xi -v yj i = 0.4v see appendix, fig. a.2 2 difference in on-state resistance between two switches (see g.4 in appendix) d r on 510 10 10 w v dd =14v, v ss =0, v dc =v dd /2, iv xi -v yj i = 0.4v see appendix, fig. a.2
iso-cmos mt8812 3-31 ? timing is over recommended temperature range. see fig. 3 for control and i/o timing details. ? typical figures are at 25c and are for design aid only; not guaranteed and not subject to production testing. crosstalk measurements are for plastic dips only, crosstalk values for plcc packages are approximately 5db better. ? timing is over recommended temperature range. see fig. 3 for control and i/o timing details. digital input rise time (tr) and fall time (tf) = 5ns. ? typical figures are at 25c and are for design aid only; not guaranteed and not subject to production testing. ? refer to appendix, fig. a.7 for test circuit. ac electrical characteristics ? - crosspoint performance -v dc is the external dc offset applied at the analog i/o pins. voltages are with respect to v dd =7v, v dc =0v, v ss =-7v, unless otherwise stated. characteristics sym min typ ? max units test conditions 1 switch i/o capacitance c s 20 pf f=1 mhz 2 feedthrough capacitance c f 0.2 pf f=1 mhz 3 frequency response channel on 20log(v out /v xi )=-3db f 3db 45 mhz switch is on; v ina = 2vpp sinewave; r l = 1k w see appendix, fig. a.3 4 total harmonic distortion (see g.5, g.6 in appendix) thd 0.01 % switch is on; v ina = 2vpp sinewave f= 1khz ; r l =1k w 5 feedthrough channel off feed.=20log (v out /v xi ) (see g.8 in appendix) fdt -95 db all switches off; v ina = 2vpp sinewave f= 1khz; r l = 1k w . see appendix, fig. a.4 6 crosstalk between any two channels for switches xi-yi and xj-yj. xtalk=20log (v yj /v xi ). (see g.7 in appendix). x talk -45 db v ina =2vpp sinewave f= 10mhz; r l = 75 w . -90 db v ina =2vpp sinewave f= 10khz; r l = 600 w . -85 db v ina =2vpp sinewave f= 10khz; r l = 1k w . -80 db v ina =2vpp sinewave f= 1khz; r l = 10k w . refer to appendix, fig. a.5 for test circuit. 7 propagation delay through switch t ps 30 ns r l =1k w ; c l =50pf ac electrical characteristics ? - control and i/o timings - v dc is the external dc offset applied at the analog i/o pins. voltages are with respect to v dd =7v, v dc =0v, v ss =-7v, unless otherwise stated. characteristics sym min typ ? max units test conditions 1 control input crosstalk to switch (for cs, data, strobe, address) cx talk 30 mvpp v in =3v+v dc squarewave; r in =1k w , r l =10k w . see appendix, fig. a.6 2 digital input capacitance c di 10 pf f=1mhz 3 switching frequency f o 20 mhz 4 setup time data to strobe t ds 10 ns r l = 1k w , c l =50pf ? 5 hold time data to strobe t dh 10 ns r l = 1k w , c l =50pf ? 6 setup time address to strobe t as 10 ns r l = 1k w , c l =50pf ? 7 hold time address to strobe t ah 10 ns r l = 1k w , c l =50pf ? 8 strobe pulse width t spw 20 ns r l = 1k w , c l =50pf ? 9 reset pulse width t rpw 40 ns r l = 1k w , c l =50pf ? 10 strobe to switch status delay t s 40 100 ns r l = 1k w , c l =50pf ? 11 data to switch status delay t d 50 100 ns r l = 1k w , c l =50pf ? 12 reset to switch status delay t r 35 100 ns r l = 1k w , c l =50pf ?
mt8812 iso-cmos 3-32 figure 3 - control memory timing diagram * see appendix, fig. a.7 for switching waveform table 1. address decode truth table this address has no effect on device status. ax0 ax1 ax2 ax3 ay0 ay1 ay2 connection 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x0-y0 x1-y0 x2-y0 x3-y0 x4-y0 x5-y0 no connection no connection x6-y0 x7-y0 x8-y0 x9-y0 x10-y0 x11-y0 no connection no connection 0 1 0 0 0 1 0 1 1 1 0 0 0 0 x0-y1 x11-y1 0 1 0 0 0 1 0 1 0 0 1 1 0 0 x0-y2 x11-y2 0 1 0 0 0 1 0 1 1 1 1 1 0 0 x0-y3 x11-y3 0 1 0 0 0 1 0 1 0 0 0 0 1 1 x0-y4 x11-y4 0 1 0 0 0 1 0 1 1 1 0 0 1 1 x0-y5 x11-y5 0 1 0 0 0 1 0 1 0 0 1 1 1 1 x0-y6 x11-y6 0 1 0 0 0 1 0 1 1 1 1 1 1 1 x0-y7 x11-y7 t rpw t spw t as t ah t dh t d t s t r t r t ds 50% 50% 50% 50% 50% 50% 50% 50% 50% reset strobe address data switch* on off
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